1. Field of the Invention
The present invention relates to an oscillator circuit constituted of a plurality of inverting and non-inverting delay circuits connected in the form of a ring.
2. Description of the Related Art
An oscillator circuit may be configured by connecting an odd number of inverting delay circuits, for example, the three inverting delay circuits DLY1, DLY2, and DLY3, in the form of the ring. FIG. 1 is a circuit diagram of a ring oscillator circuit constituted in this way, while FIG. 2 shows the configuration of an inverting delay circuit comprising inverting elements and delay elements connected to the output side of the inverting elements.
As shown in FIG. 2, an inverting element is constituted by a differential amplifier circuit. The delay element connected to the output side thereof is constituted by a transistor and capacitor forming an emitter follower. The differential amplifier circuit is constituted by transistors Q1 and Q2, resistance elements R1 and R2, and a current source I1, while the delay element is constituted by transistors Q3 and Q4, capacitors C1 and C2, and transistors Q5 and Q6.
In the differential amplifier circuit, bases of the transistors Q1 and Q2 are respectively connected to input terminals Tin and T/in, collectors are connected to a supply line of a power supply voltage V.sub.CC via the resistance elements R1 and R2, respectively, and emitters are commonly connected to the current source I1. The connection nodes formed by the collectors of the transistors Q1 and Q2 and the resistance elements R1 and R2 constitute the output nodes of the differential amplifier circuit. A current i.sub.1 is supplied by the current source I1.
In the delay element, transistors Q3 and Q4 form an emitter follower. Bases of the transistors Q3 and Q4 are respectively connected to the output nodes ND1 and ND2 of the differential amplifier circuit, while the emitters are respectively connected to the output nodes ND3 and ND4 of the delay element. The capacitor C1 is connected between the node ND3 and the supply line of the power supply voltage V.sub.CC, and the capacitor C2 is connected between the node ND4 and the supply line of the power supply voltage V.sub.CC. Both of bases of the transistors Q5 and Q6 are connected to an input terminal Tc of a control signal Sc, the collectors are respectively connected to the nodes ND3 and ND4, and the emitters are grounded via the resistance elements R3 and R4, respectively.
Input signals SA and /SA are respectively supplied to the input terminals Tin and T/in, an inverted signal /SB of the input signal SA is supplied to the output node ND1 of the differential amplifier circuit, and an inverted signal SB of the input signal /SA is output to the output node ND2.
Output signals of the nodes ND1 and ND2 are output to the nodes ND3 and ND4 by the emitter follower comprising the transistors Q3 and Q4, respectively. Potentials of the nodes ND3 and ND4 are set by the charging and discharging of the capacitors C1 and C2 in accordance with the input signal, the voltage of the node ND3 is output as an output signal /SC to an output terminal T/out, and the voltage of the node ND4 is output as an output signal SC to an output terminal Tout.
The transistors Q5 and Q6 constitute a current source for controlling charging currents i.sub.2 and i.sub.3 of the capacitors C1 and C2. Collector currents of the transistors Q5 and Q6 are determined by the control signal Sc input to the input terminal Tc. These collector currents become charging currents of the capacitors C1 and C2. Here, for example, if both of the voltages between bases and emitters when the transistors Q3 and Q4 are in an on state are Vf, voltages of the nodes ND3 and ND4 become (V.sub.CC -Vf) when the transistor Q3 or Q4 is on. When the transistor Q3 or Q4 switches from the on state to an off state, the capacitors C1 and C2 are charged by the currents i.sub.2 and i.sub.3, respectively, and voltages of the nodes ND3 and ND4 rise along with the charging of the capacitors C1 and C2. Here, if both of resistance values of the resistance elements R1 and R2 are R, an amplitude of the signal of collectors of the transistors Q1 and Q2 becomes (R.multidot.i.sub.1). When the charging to the capacitor C1 or C2 is ended, the voltage of the node ND3 or ND4 is held at (V.sub.CC -Vf-R.multidot.i.sub.1).
FIGS. 3A to 3C are waveform diagrams of parts of the delay circuit shown in FIG. 2. As illustrated, the levels of the output signals SB and /SB of the inverting element comprising the differential amplifier circuit change in accordance with the change of level of the input signals SA and /SA. The signals SB and /SB are input to the delay element, and the levels of the output signals SC and /SC of the delay circuit change in accordance with these signals. For example, when the input signal SA is at a high level, the output signal SB of the differential amplifier circuit is also held at the high level, for example, the power supply voltage V.sub.CC or a level near this, while conversely when the input signal SA is at a low level, the output signal SB of the differential amplifier circuit is also held at a low level, that is, the (V.sub.CC -R.multidot.i.sub.1) level. When the signal SB becomes a low level, the transistor Q4 turns off, and the capacitor C2 is charged, therefore the voltage of the node ND4 falls. When the signal SB switches from a low level to a high level, the transistor Q4 switches from the off state to the on state, and the capacitor C2 discharges via the transistor Q4, therefore the voltage of the node ND4 rises along with the discharge and is held at a high level, for example, the (V.sub.CC -Vf) level.
The discharging of the capacitor C2 is carried out via the transistor Q4 in the on state. The on resistance of the transistor Q4 is low and the discharge of the capacitor is fast. On the other hand, the charging of the capacitor C2 is carried out via the transistor Q6. If the charging current i.sub.3 is small, the charging time becomes longer than the discharging time. As a result, the waveform of the output signal SC of the delay element becomes asymmetrical between the rising and trailing edges as shown in FIGS. 3A to 3C. That is, the rising edge is sharp, and the trailing edge is gentle.
Similarly, the signal /SC output from the delay element has the same characteristics. By adjusting the level of the control signal Sc supplied to the bases of the transistors Q5 and Q6, the charging time of the capacitors C1 and C2 is controlled, that is, the slew rate of the fall of the signals SC and /SC is controlled, and a delay time td of the delay element is controlled.
A clock signal CLK of a cycle (2n.times.td) is obtained by the oscillator circuit by using an odd number n of stages of delay circuits comprising such inverting elements and delay elements and connecting them in the form of a ring.
In the oscillator circuit of the related art, the slew rate of the rising edge of the output signal of the delay circuit is not controlled by the control signal Sc and is substantially fixed. The delay time of the delay circuit is controlled in accordance with only the slew rate of the trailing edge, therefore a large delay time cannot be formed while enhancing the control property of the delay time. As a result, in the oscillator circuit of the related art, there were the disadvantages that the control property was poor and the range of variation of the frequency could not be increased.